The present invention relates to channel stops and trench dielectric isolation structures for electrically isolating semiconductor devices and components in monolithic integrated circuits. The invention also relates to techniques for forming such channel stop structures alone or in combination with trench isolation structures. A layer of doped glass is formed on vertical sidewalls in the semiconductor substrate, then the dopant is driven into the substrate sidewall, taking advantage of the segregation of conductivity-altering impurities, such as boron, between the silicon and the glass to provide a narrow boron channel stop in the substrate sidewall.
Presently, VLSI integrated circuit structures are being scaled to ever smaller minimum feature sizes and separations to provide greater device densities and faster operational speeds. The minimum feature size and the minimum feature separation depend in part upon the minimum mask dimensions that are available for the particular lithographic process. These, in turn, depend upon various factors, including the lithographic process itself, the wafer topography, and the feature change associated with the particular process step (etching, implanting, diffusion).
It is highly desirable in integrated circuit (IC) processing to form channel stops having very small lateral dimensions which are consistent with the close packing necessary for VLSI and future device technologies. For the same reason, it is desirable to form trench isolation structures having very small lateral dimensions. FIG. 1 illustrates a desirable NMOS FET 11, which incorporates narrow channel stops 12 along the vertical semiconductor sidewalls of trench structures 13. The NMOS FET 11 is part of a CMOS (cmplementary MOS) structure and is formed in the p-well 14 of an n-type epitaxial layer 15. The FET 11 includes heavily doped source and drain regions 16 and 17 and LDD (lightly doped drain) regions 18, all of which are self-aligned with the conductively doped polysilicon gate 19. The FET IC structure also includes gate oxide sidewall spacers 21, interlevel dielectric 22, and aluminum interconnect 23. This is only one possible application of the illustrated channel stop channel stop-trench structure to various NMOS, PMOS, CMOS, bipolar and other integrated circuit structures.
Unfortunately, the dual constraints imposed by the lithographic process and the particular processing step are reflected in the unsuccessful attempts to form narrow channel stops using conventional technology. The prevalent techniques for forming channel stops involve the application of conventional lithographic masking and doping and thus are subject to the relatively large alignment tolerances associated with conventional lithographic masking, and variability in lateral diffusions of the channel stop regions during dopant drive cycle. For such reasons, conventional techniques are not suitable for forming the narrow channel stop structure shown in FIG. 1.
Predeposition and drive-in using a solid source are, of course, known, but to our knowledge are used in the art with conventional masking and/or drive-in techniques which are not amenable to forming thin diffusion regions on the vertical walls of trench isolation structures. For example, Briska et al U.S. Pat. No. 4,313,773 teaches predeposition and drive-in using an SiB.sub.6 solid source. In particular, a layer of SiB.sub.6 is selectively formed on an exposed silicon substrate using a conventional silicon dioxide deposition mask, and is followed with the deposition of a boron rich silicon dioxide layer and the deposition of a borosilicate glass layer. After boron is diffused into the silicon substrate with an anneal cycle, the outer layers are removed and the boron dopant is driven further into the underlying epi substrate by heating the substrate in an oxidizing ambient.
Ho et al, U.S. Pat. No. 4,209,350, forms channel stops using deposition and reactive ion etching, and avoids the use of a lithographic mask, per se, in defining the width of the channel stops. The horizontal/lateral width of the channel stop diffusion regions is defined by the corresponding dimension of an overlying, highly doped layer which is the source of the impurity dopant for the diffusion region. The Ho et al technique is illustrated in perhaps its broadest aspect by the formation of the channel stops 27 shown in FIG. 2. These channel stops are formed as follows. First, a diffusion barrier layer 28 of silicon dioxide or the like is formed on the semiconductor substrate 29. Reactive ion etching (RIE) is then applied to form openings 31 in the diffusion barrier layer 28. Thereafter, a doped insulator or polysilicon source layer is deposited on the diffusion barrier layer 28 and reactive ion etched to remove the horizontal portions of the layer and leave only the vertical sections 32 on the sidewalls of the diffusion barrier layer 28. The substrate channel stops 27 are then formed by vertical diffusion from the bottom of residual sections 32. The deposited thickness of dopant source layer 32 on the sidewalls of diffusion barrier layer 28 determines the width of the channel stops 27.
In short, Ho et al. uses the sidewalls of a first layer to locate a second doped layer for vertical diffusion into an underlying substrate. Diffusion barrier layer 28 blocks lateral diffusion from the layers 32 so that the diffusion is directed vertically downward into the substrate 29.
In another aspect, shown in FIG. 3, the Ho et al patent forms the first, locating layer 28 and the second, dopant source layer 32 in the channel region of an FET device between the substrate isolation trenches 33. During the drive-in of the n.sup.+ source and drain 35 and 36, opposite conductivity p-regions 37 are diffused from the dopant source layer 32 into the substrate to form a narrow channel at 38.
In other aspects, the Ho et al process is used to form collector and collector reach-through regions of bipolar devices. Here, again, the patent refers to the use of the sidewalls of a first, insulating layer to position a second, doped layer for vertical diffusion into an underlying substrate. The patent bypasses the use of a lithographic mask process in defining the width of the channel stops and, instead, uses the lateral thickness of this deposited vertical source layer for this purpose. However, the relatively narrow width channel stops as practiced in FIG. 3 are accomplished at the cost of using a selfaligned gate process.
Note that with the exception of very shallow channel stop dopant penetrations, the lateral diffusion during the vertical diffusion of the channel stops would seem to eliminate the original, relatively small lateral dimension of the channel stop.
In view of the above discussion, it is an object of the present invention to provide a channel stop fabrication process and structure which avoids the dual prior art constraints, i.e., photolithographic masking and vertical diffusion drive-in, on the minimum feature size of channel stops.
It is a corollary object of the present invention to provide a channel stop fabrication process which forms the channel stops along the vertically disposed walls of trench isolation structures and uses lateral drive-in of the dopant to define the channel stop.